Typically an integrated circuit will comprise the functional circuitry needed to perform the processing functions of the integrated circuit, along with interface circuitry (often referred to as input/output (I/O) circuitry) for providing an interface between the functional circuitry and components external to the integrated circuit. The interface circuitry will typically consist of a plurality of interface (I/O) cells used to implement the input/output requirements of the integrated circuit.
Each interface cell typically incorporates a power supply line section extending across its width, and configured to cooperate with the power supply line section of other interface cells (for example by placing a plurality of interface cells side-by-side within the interface circuitry) in order to provide a power supply line structure which is shared by the interface cells and used to provide a power supply to the interface components of the interface cells.
In addition to providing the required power supply, or power supplies, to the interface components of the interface cells, the power supply line structure has to be sized sufficiently to support a current carrying constraint of the interface circuitry. In particular, the I/O cells will typically include electrostatic discharge (ESD) components used to provide ESD protection during ESD events, and as a result the various lines within the power supply line structure need to be sized sufficiently to manage the relatively large currents that arise during such ESD events.
Often the various supply lines of the power supply line structure are provided within the upper metal layers (also referred to as the thick metal layers) of the integrated circuit where they can be sized appropriately to manage the current drawn during such ESD events. However, this results in the area occupied by the power supply line structure becoming relatively large, and in particular the sizing requirements of the power supply line structure are becoming a limiting constraint when seeking to reduce the size of the I/O cells.
As the size of integrated circuits continues to decrease, there is an ever increasing pressure to reduce the size of the I/O cells used to form the interface circuitry of the integrated circuit. This pressure applies irrespective of how the interface circuitry is arranged within the integrated circuit. For example, in area array System-on-Chips (SoCs), several clusters of I/O cells are distributed within the integrated circuit. Alternatively, in an I/O ring arrangement, the interface circuitry takes the form of an I/O ring around the periphery of the integrated circuit and surrounding the functional circuitry of the integrated circuit. In all of these various arrangements, the above-mentioned current carrying constraints (typically due to ESD protection requirements) have limited the reductions that can be made in the size of the power supply line structure provided within the I/O cells, thus limiting the extent to which the area occupied by the I/O circuitry can be reduced, and hence limiting the reductions that can be made in the size of the integrated circuit.
Accordingly, it would be desirable to provide an improved arrangement for providing the necessary power supplies to the interface circuitry of an integrated circuit, whilst enabling the current carrying requirements to continue to be met.